1. Field of the Invention
This invention relates generally to a dummy cells utilized in a high accuracy self-timing circuits in dual-port SRAM (Static Random Access Memory), and particularly relates to a dummy cells utilized in a high accuracy self-timing circuits in dual-port SRAM which operates with high speed and low power.
2. Description of the Prior Art
In a prior art static random access memory where each memory cell is supplied with a voltage through a bit line from a circuit that serves as a load of the driving transistor of the cell through a gate-controlled coupling transistor, a voltage developed at the bit line is determined by the discharging current passing through the ON coupling transistor and the driving transistor of the cell. Since the operational characteristics of these transistors vary with device variabilities due to manufacture and temperature variations, the memory is designed with a safety margin to accommodate such factors, and hence, the operational performance of the memory cannot be exploited to the fullest extent.
Especially in designing modern embedded SRAM, the self-timing control circuits become more popular for speeding up the access time and cycle time or employing latch type sense amplifiers due to the trend of high-speed device and low power application. However, the accuracy of the self-timing control circuits is getting worse as the process shrinking and narrow width device employed in memory bit cells. Moreover, the accuracy of the self-timing circuit is also vulnerable to the minor process variation. The timing inaccuracy of the self-timing circuit is greatly attributed to the activity of the bit-lines.
In a conventional case of a self-timing circuit, only the capacitance of bit lines is simulated when tracking the activity of bit lines. Though, in some advanced design, it also simulates the resistance of the bit line as well, the current source utilized to drive the dummy bit line is not as accurate as the real memory cell. In other words, the voltage drop on the dummy bit line can not be coincide with the voltage drop on the bit line of the real memory cell. So in most design of self-timing circuit, the simulation of bit line loading and access activity are not accurate enough.
As the process shrinks, and narrow width devices are employed nowadays, the differences in electrical characteristics between mid-size device and narrow width device become more critical. Besides, for embedded memory in logic process, the logic SPICE model provided by foundry does not usually reflect the activity of memory cell with very high accuracy, especially when they have some extra processes for embedded memory cells. Therefore, the less accurate current source for the dummy bit line could cause timing inaccuracy than before.
To illustrate the conventional self-timing circuit utilizing the dummy bit-line in the embedded memory cell, the configuration of the control circuit as well as the pattern of the dummy memory cells are shown in FIG. 1. As an example, the control circuit in FIG. 1 can be the word line pulse generator 10, and the word line pulse is transmitted from terminal dmy_wl of word line pulse generator 10 to the inverter 11. Then the inverter 11 precharges the loading composed of N dummy half-memory cells. The bit line 13 is connected to the output terminal of the inverter 11; also, the bit line 13 is connected to the memory cell column 15 that is composed of a plurality of memory cells acting as the loading of the inverter 11. Each component of the plurality of memory cells is a memory cell 17 (or a half memory cell). The memory cell 17 is a dual-port memory cell whose circuitry is shown in FIG. 2, in which the word line WL1 and the word line WL2 are respectively connected to the gates of the transistors N4, N5, and the gates of the transistors N6, N7. The source of the transistors N4 and N6 are coupled at a point DATA, and the drain of the former are connected to the bit line BL and BL2 respectively. Similarly, the source of the transistors N5 and N7 are coupled at a point ZDATA, and the drain of the former are connected to the inverse of the bit line ZBL and ZBL2 respectively. The gate of the transistor P0 is coupled to the gate of the transistor N2 through the point NODE1; in addition, the drain of the transistor P0 is coupled to the drain of the transistor N2 at the point DATA. The source of the transistor P0 is coupled to Vdd and the source of the transistor N2 is coupled to the voltage Vss. The gate of the transistor P1 is coupled to the gate of the transistor N3 through the point NODE2; in addition, the drain of the transistor P1 is coupled to the drain of the transistor N4 at the point ZDATA. The source of the transistor P1 is coupled to Vdd and the source of the transistor N3 is coupled to the voltage Vss. Besides, a wire WIRE1 couples the point DATA to the point NODE2, and a wire WIRE2 couples the point ZDATA to the point NODE1.
In the other example of the prior art dummy memory cell array, the inverter 11 can be replaced with a transistor such as a NMOS, and the circuitry is shown in FIG. 1B. To obtain a high-speed element, time margin should be reduced to a minimum. So it is better to track the voltage on the bit line of the normal memory cell array, and then the time margin is saved. However, no matter what type of the prior art dummy memory cell array is used, the voltage on the dummy bit line can not exactly track the voltage on the normal memory cell due to the following reasons. First, the current source in the prior art dummy memory cell is inverter or transistor, in addition, the gate width and gate length of the current source as well as the layout utilized in the prior art is different from that of the normal memory cell. So the discharge current on the normal bit line is not the same as that on the dummy bit line. Secondly, the process that utilized to fabricate the inverter NMOS is different from that of the memory cell.
In addition, the design of the memory cell concerning the pattern of the dummy bit line and the loading does not take the worst case of loading into account. Thus, when a plurality of loading memory cells coupled to the bit line are logic "1" or high voltage, and both WL1 and WL2 are accessed, the voltage on the dummy bit line can not exactly track the voltage on the bit line of the normal memory cell. Especially, when the number of the memory cell continuously increases with the trend of high-density element, the difference of loading capacitance will seriously affect the precision of tracking the voltage on the normal bit line. Due to the reasons mentioned above, it is necessary to improve the dummy memory cell to obtain a high-speed element.